1. Field of the Invention
The present invention relates to a burst-mode receiving apparatus. More particularly, the present invention relates to a noise-resistive, burst-mode receiving apparatus and a method for recovering a clock signal and data therefrom.
2. Description of the Related Art
In general, a receiving apparatus of a communication system adopts a phase locked loop (PLL) to recover a clock signal and data therein. The PLL is capable of minimizing the swaying of an edge of an input signal caused by a vibration or outer shocks, and thus, it is possible to recover a clock signal having the optimal decision timing in the receiving apparatus.
However, unlike the receiving apparatus adopted in general communication systems, it is difficult to recover a clock signal and data with a conventional burst-mode receiving apparatus using the PLL. This difficulty arises because the frequency of the input signal input into the receiving apparatus is different from the frequency of a system clock signal that is used in the burst-mode receiving apparatus. Further, since the specific time when the input signal is to be input is difficult to determine, intervals between burst cells are bits that cannot be continuously calculated, irrespective of the system clock signal. For this reason, the conventional burst-mode receiving apparatus adopting a PLL can be used without any particular inconvenience in a case where the input signal is changed slightly within a tracking range after the PLL is locked. However, if the PLL becomes unlocked due to a large difference between the phase of an interval between the present cell and the next cell and the phase of a clock signal recovered at the present cell, acquisition time is required until the unlocked PLL becomes locked again. Accordingly, the PLL is not available in the conventional burst-mode receiving apparatus that is designed to speedily recover a clock signal.
Meanwhile, in a conventional burst-mode receiving apparatus that is capable of recovering a clock signal and the data thereof without a PLL, an input signal and a clock signal are controlled to be in phase by delaying the input signal, generating the clock signal at the beginning of inputting data, or selecting either a clock signal that leads an input signal or that is in phase with the input signal among multi-phase clock signals. Of these methods, the method of selecting a desired clock signal among the multi-phase clock signals is mainly used. At this time, since the receiving rate of an input signal is difficult to determine, the conventional burst-mode receiving apparatus uses a self-generated system clock signal. Thus, in the event that the input signal is successively input with 0 or 1, there is a higher probability that the number of successive bits is erroneously recognized, and a time delay of at least 3 bits may elapse before the clock signal is recovered.